As the size of semiconductor devices continues to shrink, the manufacturing of these devices becomes increasingly difficult. One of the challenges in manufacturing these devices is to accurately pattern the structures from different layers using lithography. For example, spacing between adjacent fin field effect transistor (FinFET) devices are decreasing such that patterning and aligning structures for the adjacent FinFETs become challenging. Exemplary challenges include growing epitaxy layers in the source/drain regions of adjacent FinFETs without merging the epitaxy layers from different fins and patterning gate electrodes of the adjacent FinFETs next to one another.